1. Field of the Invention
The present invention relates generally to the manufacture of semiconductor integrated circuit devices, and more specifically to a method for providing improved isolation and noise immunity for field effect devices.
2. Description of the Prior Art
Bipolar and CMOS technologies are increasingly being combined in a single integrated circuit device. Such a combination can provide the benefits of low power CMOS circuitry on most of the chip, with the high input/output driving capacity of bipolar devices. Such combined devices can result in a small, high speed, low power integrated circuit.
In dynamic random access memories (DRAM), the memory array is fabricated from N-channel field effect devices. Static random access memories (SRAM) use N-channel devices with polycrystalline silicon load devices in the memory array. Both types of memories often use CMOS in the periphery of the device for providing decode functions, sense amplifiers and so forth. Bipolar transistors are generally used only for input/output interfaces.
Generally, the memory cell and peripheral N-channel transistors are formed in a P-well with a P.sup.+ buried layer underneath. Bipolar NPN transistors are built in an N-well with an N.sup.+ buried layer for a collector. Such transistors require the use of a P-type substrate. P-channel transistors are formed in an N-well with an N.sup.+ buried layer for improved resistance.
For high density memory devices, various types of low level noise cause significant problems with device operation. This noise can be caused by alpha particle events and switching noise from the peripheral circuitry. Also, a great deal of noise can be generated by the input/output circuitry.
In addition, latch-up has always been a major concern in CMOS devices. This is especially true in the peripheral circuitry.
It would be desirable for a semiconductor device fabrication technique to provide improved noise immunity and increased protection from latch-up.